The present invention relates to a semiconductor memory device having memory cells, and particularly, to a semiconductor memory device having memory cell arrays divided longitudinally and laterally into four core sections.
To reduce operational currents of a semiconductor memory device, memory cell arrays are dispersively activated. In recent years, to further reduce operational currents, all memory cell arrays are divided into two groups, one of the two groups is selected, and memory cell arrays belonging to the selected group are dispersively activated.
FIG. 1 shows a structure of a conventional semiconductor memory device. In the following, same components are denoted by same reference symbols, and reiteration of those components will be omitted.
Core sections 1 to 4 generally have equal memory capacities. The core sections 1, 2, 3 and 4 are respectively positioned at the upper left, lower left, upper right, and lower right of a chip CP.
An address buffer 11 is provided at an area between the core sections 3 and 4, for example. The address buffer 11 is supplied with external address signals A0 to A11 from a pad in the chip CP and generates control signals RAt11 and RAc11 from, for example, an address signal A11.
Core section buffers 5 to 8 are arranged adjacent to the core sections 1 to 4, respectively. The core section buffers 5 and 6 are supplied with a control signal RAt11 outputted from the address buffer 11, and the core section buffers 7 and 8 are supplied with a control signal RAc11 outputted from the address buffer 11. The core section buffers 5 to 8 respectively activate the core sections 1 to 4 in accordance with the control signals RAt11 and RAc11.
Each of the core sections 1 to 4 comprises a plurality of memory cell arrays 10, sense amplifiers 9 connected to the memory cell arrays 10, and circuits (not shown) for selecting memory cells in accordance with a signal, such as an array decoder and a row decoder. As shown in FIG. 1, the memory cell arrays 10 and sense amplifiers 9 are disposed alternately, and each of the sense amplifiers 9 is shared by two memory cell arrays 10. The array decoder selects one or more memory cell arrays in a core section to be activated by an instruction, in accordance with an upper bit of an address signal supplied through a core section buffer. The row decoder selects a word line of the memory cell array selected by the array decoder, in accordance with a lower bit of an address signal supplied through a core section buffer.
Peripheral circuits 12 such as row decoders and column decoders described above are provided between the core sections 1 and 2, 3 and 4, 1 and 3, as well as 2 and 4.
A plurality of pads 50 are provided at the areas where the peripheral circuits 12 are provided such that the pads are disposed laterally, for example. A part of the pads are used as power supply pads.
The following will be an explanation of a method of activating memory cell arrays divided into four core sections.
An address buffer 11 generates control signals RAt11 and RAc11 relating to rows, from a bit A11 of an external address signal. The control signal RAc11 is an inverted signal of the control signal RAt11. In the following, xe2x80x9ccxe2x80x9d indicates an inverted signal and xe2x80x9ctxe2x80x9d indicates a non-inverted signal.
Where the signal RAt11 is of a selected state and the signal RAc11 is of a non-selected state, the upper left core section 1 and the lower left core section 2 are selected. In this state, the upper right core section 3 and the lower right core section 4 are not selected and deactivated.
Further, memory cells of each of the selected core sections 1 and 2 are divided into two groups, and memory cells belonging to one of the groups are activated in accordance with an upper address of the address signal. FIG. 1 shows a semiconductor memory device in this state. In the figure, those memory cell arrays 10 and sense amplifiers 9 which are hatched by oblique lines indicate activated arrays and sense amplifiers.
Where the signal RAt11 is of a non-selected state and the signal RAc11 is of a selected state, the memory cells of the upper right core section 3 and the lower right core section 4 are activated.
When a bit line is charged or discharged by sense amplifiers, e.g., when the potential of a bit line is changed from xc2xdxc3x97Vcc to Vcc or VSS, noise is generated by the switching operation of a transistor for connecting a sense amplifier with a bit line.
In a conventional semiconductor memory device, activated cell arrays are concentrated at the left or right half of the semiconductor memory device. When the core sections 1 and 2 are activated, noise is generated concentrically in the left half of the semiconductor memory device. When the core sections 3 and 4 are activated, noise is generated concentrically in the right half of the semiconductor memory device.
The noise thus generated is reflected on power supply lines or the like and influences the operation of input pins and peripheral circuits in the vicinity of the activated core sections. Specifically, the potential of power supply lines supplied with a voltage VSS rises thereby hindering supply of a VSS level. As a result, threshold voltages and the like of elements forming sense amplifiers and peripheral circuits are changed, and associated circuits cause operation errors.
In FIG. 2, it is supposed that a power supply pad 13 supplied with a voltage VSS is provided in the left side of an area between the core sections 1 and 2, and a power supply pad 14 supplied with a voltage Vcc is provided in the right side of an area between the core sections 3 and 4. FIG. 2 shows a case where the core sections 3 and 4 are activated and arrows in this figure indicate main flows of currents to a power supply pad.
Power supply lines from the power supply pad 13 to the core sections 3 and 4 are longer than power supply lines from the power supply pad 13 to the core sections 1 and 2. Therefore, a voltage drop caused in the power supply lines is large when the core sections 3 and 4 are activated. An influence from the voltage drop in the power supply lines when the core sections 3 and 4 are activated is therefore greater than that when the core sections 1 and 2 are activated.
In FIG. 3, it is supposed that a power supply pad pair 15 respectively supplied with voltages Vcc and Vss is provided in the left side of an area between the core sections 1 and 2, and another power supply pad pair 16 respectively supplied with voltages is provided in the right side of an area between the core sections 3 and 4. Arrows in this figure indicate main flows of currents to the power supply pads.
In this case, a length of power supply lines from the left power supply pad pair 15 to the core sections 1 and 2 are substantially the same as that of the power supply lines from the right power supply pad pair 16. Therefore, unlike the example shown in FIG. 2, an influence from a voltage drop does not vary much depending on the positions of activated core sections.
However, when the core sections 1 and 2 are activated, currents concentrically flow through the left power supply pad pair 15. When the core sections 3 and 4 are activated, currents concentrically flow through the right power supply pad pair 16.
Generally, a semiconductor chip is sealed on a lead frame by resin and pads such as power supply pads are connected to inner leads by bonding wires thereto. A packaged semiconductor device is set on a board and outer leads are connected to wires on the board. Therefore, a pad supplied with a voltage VSS is applied with inductance from the lead frame and the wires on the board. Where L is the inductance applied to the power supply pad, noise is expressed as Lxc3x97di/dt. Therefore, as described above, large noise is generated by the inductance when a current concentrically flows through one pair of power supply pads.
Thus, power supply noise caused by resistance or inductance reaches a level that significantly influences the operation of circuits.
The present invention has an object of reducing generation of noise in a semiconductor memory device in which memory cell arrays are activated dispersively.
A semiconductor memory device according to the present invention comprises at least four memory cell arrays arranged in matrix, wherein the memory cell arrays are activated to prevent from simultaneously activating memory cell arrays arranged longitudinally.
Specifically, a semiconductor memory device has a following structure.
A semiconductor memory device according to the present invention comprises a first core section including a plurality of memory cell arrays; a second core section including a plurality of memory cell arrays and provided below the first core section; a third core section including a plurality of memory cell arrays and provided in a right side of the first core section; and a fourth core section including a plurality of memory cell arrays and provided in a right side of the second core section, wherein at least a part of the memory cell arrays of the first core section and at least a part of the memory cell arrays of the fourth core section are simultaneously activated, and at least a part of the memory cell arrays of the second core section and at least a part of the memory cell arrays of the third core section are simultaneously activated.
Another semiconductor memory device according to the present invention comprises a first core section including a plurality of memory cell arrays; a second core section including a plurality of memory cell arrays and provided below the first core section; a third core section including a plurality of memory cell arrays and provided in a right side of the first core section; a fourth core section including a plurality of memory cell arrays, and provided in a right side of the second core section; and an address buffer having an input terminal supplied with an address signal, for outputting a first or second activation signal in accordance with a part of the address signal, the first activation signal making the first and fourth core sections be activated and the second activation signal making the second and third core sections be activated.
Preferred embodiments of the present invention are as follows.
(1) A first power supply line connected to the first and third core sections and provided along lower edges of the first and third core sections; a second power supply line connected to the second and fourth core sections and provided along upper edges of the second and fourth core sections and below the first power supply line; and a wire for connecting the first and second power supply lines with each other at an area between the first and second core sections and-at an area between the third and fourth core sections are further provided.
(2) In the above (1), a plurality of pads are provided between the first and second power supply lines and the wire is provided at an area between the pads.
(3) Each of the first to fourth core sections includes a core section buffer having an input terminal supplied with another part of the address signal and with the first or second activation signal which activates the core section corresponding to the core section buffer, for outputting the address signal supplied, in accordance with the activation signal supplied, an array decoder for selecting one of the plurality of memory cell arrays forming the core sections, with use of an upper bit of the address signal outputted from the core section buffer, and a row decoder for selecting one of a plurality of word lines of the memory cell array selected by the array decoder, with use of a lower bit of the address signal.
(4) A first output buffer is shared by the first and second core sections and a second output buffer is shared by the third and fourth core sections.
(5) In the above (1), each of the plurality of memory cell arrays has at least two sub-memory cell arrays, and when one of the two sub-memory cell arrays is activated, another sub-memory cell array is deactivated.
(6) In the above (1), each of the plurality of memory cell arrays has at least two sub-memory cell arrays, and each of the sub-memory cell arrays is operated independently.
(7) In the above (1), a sense amplifier for sensing and amplifying data from the plurality of memory cell arrays is shared by adjacent memory cell arrays.
According to the present invention, core sections arranged longitudinally and laterally are activated diagonally, and activated memory cell arrays are dispersed. Therefore, influences from noise can be reduced and are prevented from affecting the operation of circuits.
Also, since activated core sections are dispersed, heat generation during operation is also dispersed. Accordingly, the present invention is particularly advantageous when the heat generation amount is large, e.g., in case of operation at a high frequency.
Additional objects and advantages of the present invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the present invention. The objects and advantages of the present invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinbefore.